Design of a High Complexity Superscalar Microprocessor with the Portable IDPS ASIC Library

This paper presents the design pow for a Superscalar VLIWmicroprocessorusing the 0.8 p CMOS portable ASIC library developed in the framework of the ESPRIT2 IDPS project. A ful l set of cell libraries and macro-block generators have been used, in order to achieve fast design cycle, and still maintains a high level of integration and performance. The final circuit contains about875 000 transistors with a die size of 14.6 * 14.6 mm2. The chip design and verification have been performed with new advanced CAD tools developed in the IDPSproject. The layout uses a symbolic approach in order to provide process independence. The package is a 428-pin PGA.